Reference is made to FIG. 1 which is a schematic diagram of a standard eight transistor (8T) memory cell 10 known in the art for use in a dual port register file (DPRF) memory. The cell 10 includes two cross-coupled CMOS inverters 12 and 14, each inverter including a series connected p-channel and n-channel transistor pair. The inputs and outputs of the inverters 12 and 14 are coupled to form a latch circuit having a true node 16 and a complement node 18.
The cell 10 further includes two transfer (pass gate) transistors 20 and 22 whose gate terminals are coupled with a write word line node (for the write word line (WWL)) and are controlled by the signal present on the WWL. Transistor 20 is source-drain connected between the true node 16 and a node associated with a true write bit line (WBLT). Transistor 22 is source-drain connected between the complement node 18 and a node associated with a complement write bit line (WBLC). The write bit lines WBLT and WBLC, along with transistors 20 and 22, form a write port for the cell 10 through which data present on the write bit lines WBLT and WBLC, in response to actuation of the write word line WWL, is written to and stored by the true node 16 and a complement node 18 of the latch circuit.
The cell 10 still further includes a transistor 24 whose gate terminal is coupled to the complement node 18 (it being understood that transistor 24 could alternatively be coupled to the true node 16). The transistor 24 is source-drain connected between a reference voltage (in this case a low voltage VL, such as ground) and an intermediate node 26. A transistor 28 is source-drain connected between the intermediate node 26 and a node associated with a read bit line (RBL). The gate terminal of transistor 28 is coupled with a read word line node (for the read word line (RWL)) and is controlled by the signal present on the RWL. The read bit line RBL, along with transistors 24 and 28, form a read port for the cell 10 through which the data value stored by the true node 16 of the latch circuit, in response to actuation of the read word line, is read from the latch circuit and output to the read bit line RBL.
The source terminals of the p-channel transistors in each inverter 12 and 14 are coupled to receive a high source voltage at a high voltage VH node, while the source terminals of the n-channel transistors in each inverter 12 and 14 are coupled to receive a low source voltage at a low voltage VL node. The high voltage VH and the low voltage VL comprise a power supply set of voltages for the cell 10. Conventionally, the high voltage VH is a positive voltage (for example, >=0.7V) and the low voltage VL is a ground voltage (for example, 0V). In an integrated circuit including the cell 10, this power supply set of voltages may be received at pins of the integrated circuit, or may instead be generated on chip by a voltage converter circuit which receives some other set of voltages received from the pins of the chip.
It will thus be recognized by those skilled in the art that the cross-coupled CMOS inverters 12 and 14 along with access transistors 20 and 22 constitute the well known six transistor (6T) static random access memory (SRAM) cell which in a single port SRAM supports storing, reading and writing of data, but in a DPRF memory is only used for storing and writing of data. In a DPRF memory, the transistors 24 and 28 constitute a read port for accessing stored data from the 6T SRAM.
Operation of the cell 10 will now be described.
When in idle mode, the following logic level condition is maintained: WWL=logic low; RWL=logic low; WBLT=logic high; WBLC=logic high; and RBL=logic high.
When operating to write a logic low (“0”) into the latch, the following logic level condition is created: WWL=logic high; WBLT=logic low; and WBLC=logic high. The condition on RWL and RBL does not matter.
When operating to write a logic high (“1”) into the latch, the following logic level condition is created: WWL=logic high; WBLT=logic high; and WBLC=logic low. The condition on RWL and RBL does not matter.
When operating to read from the latch, the following logic level condition is created: RWL=logic high; and RBL=float at logic high. The read circuitry is to be designed such that the condition on the WWL should not impact the read operation if both WBLT and WBLC are logic high. However, when a write operation is also happening on the same address location as a read operation (referred to in the art as a concurrent address access), implying that the WWL is at logic high and one of WBLT and WBLC is at logic low, the read operation may not be guaranteed to give any predictable data, and this is an acceptable system constraint. But in a non concurrent address access, depending on the stored data, RBL discharges (if the complement node 18 is logic high and the true node 16 is logic low) or RBL remains at logic high (if the complement node 18 is logic low and the true node 16 is logic high).
Reference is now made to FIG. 2 which is a block diagram of a dual port register file (DPRF) memory array 30. The array 30 includes a plurality of cells 10 arranged in a matrix format. The number of cells 10 included in the array 30 can widely vary depending on the circuit designer's needs. The high voltage VH and the low voltage VL of the power supply set of voltages is applied to the array 30 and distributed over the array in a manner well known to those skilled in the art to the individual ones of the included cells 10 (for application to the source terminals of the p-channel and n-channel transistors as shown in FIG. 1). The block diagram of FIG. 2 further shows the orientation of the bit lines and word lines; with the cells 10 in a same column of the array sharing the ports for the WBLTx (x=1, 2, 3, etc.), WBLCx (x=1, 2, 3, etc.) and RBLx (x=1, 2, 3, etc.), and with the cells 10 in a same row of the array sharing ports for the WWLy (y=1, 2, 3, etc.) and RWLy (y=1, 2, 3, etc.). The array 30 may be arranged, for example, with “w” words and “b” bits, organized as a column mux of “m” having “w/m” rows and “b*m” columns.
A problem arises when a DPRF memory array 30 is organized as column mux>1. For such memory, it is expected to be allowed to perform a write operation on any row for example at a column “i”, and to simultaneously perform a read operation on the SAME row, but in another column “j” (again, this is referred to in the art as a concurrent row address access, since only the row address is the same between the read port and the write port, while the column address is different). It should also be noted that, even though the row addresses are same, the complete read port and write port addresses are different. Reference is now made to FIG. 3 which shows two cells 10(i) and 10(j) of same I/O bit, in a same row (these cells need not be adjacent, the illustration adjacency being exemplary only and for ease of showing the problem). FIG. 3 further illustrates the logic level condition on the various ports of the two columns (i and j) in the selected row when the simultaneous write (to the cell in column<i>) and read (to the cell in column<j>) is made on a same row (i.e., a concurrent row address access).
Because WWL=logic high, one of either the true node 16 or complement node 18 in column<j>, depending on which one is currently storing a logic low level (“0”) will experience a bounce to a value greater than the logic low level (“0”) because of a connection through the actuated pass transistors 20 or 22 to the WBLT or WBLC respectively, as WBLT and WBLC are either driven to logic high or are floating at logic high. This is a well known phenomenon which constrains the stability of the six transistor (6T) SRAM cell.
Considering a case when a logic low (“0”) is expected to be read from column<j> (i.e., the complement node 18 is logic high and the true node 16 is at logic low), the bounce due to concurrent row address access, as described above, will happen on true node 16 of column<j>. In this scenario, the RBL of column<j> will discharge as expected, as it was precharged to logic high. The bounce on the true node 16 has no bearing on the success of this read operation, as the complement node 18 does not observe any change in voltage level due to limited bounce on true node 16 and will continue to stay at logic high.
However, for the case when a logic high (“1”) is expected to be read from column<j> (i.e., the complement node 18 is logic low and the true node 16 is at logic high), the RBL of column<j> is not expected to discharge, but rather is expected to stay precharged to logic high as it was at the beginning of the cycle. The bounce due to concurrent row address access, as described above, in this case will happen on complement node 18 of column<j> resulting in a voltage higher than 0 on this node. This bounce on complement node 18 of column<j> is a concern. In this scenario the transistor 24, which is expected to be off because of logic low level on its gate resulting in no discharge of RBL, may instead start to operate in a strong sub-threshold region (or in certain corner cases, even turn on) because of a value higher than logic low (“0”) present at the complement node 18 due to the bounce. This will lead to an unintended discharge of the RBL, possibly leading to a mistaken reading of a logic low (“0”) from the latch circuit instead of a logic high (“1”) if the unintended discharge of RBL exceeds the threshold of a next detecting stage (i.e., the discharge of RBL is to an extent that the subsequent stage reads RBL as logic low).
Reference is now made to FIG. 4 which illustrates a timing diagram showing voltage of the read bit line as a function of time during a read operation. As can be seen with reference to line 50 showing bit line discharge, at the point in time 52 for bit line level evaluation, there is a problem with a read of a logic high (“1” referred to as “Read-1”) for the fastest read port with noise injected by the write port during the concurrent row address access scenario because of an unintended discharge of RBL to at least a range of uncertainty with respect to making a logic high/low determination by the next stage. Indeed, depending on location of the point in time 52 for bit line level evaluation, the unintended discharge of RBL due to the bounce problem could cause the RBL voltage to fall into the detect as logic low (“0”) range. Conversely, as shown with reference to line 54 showing bit line discharge, without noise injected by the write port, as would be the case when the write port is either not accessing any location or is accessing a different row of the DPRF matrix, at the point in time 52 for bit line level evaluation there is no problem with a read of a logic high (“1”) because the RBL has not discharged even to the uncertainty range. To complete the analysis, line 56 showing bit line discharge shows that there is no issue with respect to reading a logic low (“0” referred to as “Read-0”) for the slowest read port because sufficient RBL discharge occurs under all cases of access by the write port.
To summarize, there is a problem with respect to noise induced on the read port of a DPRF memory cell by its write port in a specific condition of operation (namely, concurrent row address access) because the transistor 24 of the read port begins operating in a strong sub-threshold/weakly on region leading to an unwanted discharge of the read bit line RBL when there is a bounce in the gate voltage of transistor 24. This can potentially lead to an incorrect read operation, and this problem poses a limit on the minimum operating voltage of the read port. It is important to note that the foregoing problem is not solvable by simply changing the timing position for bit line level evaluation (reference 52). For example, moving the point in time 52 for bit line level evaluation back (i.e., closer to the time of read wordline RWL actuation) as shown at 58 may solve the problem with respect to line 50, but will introduce a problem of uncertainty with respect to line 56 corresponding to the case when RBL is expected to discharge and be detected as logic low by next stage. Conversely, moving the point in time 52 for bit line level evaluation forward (i.e., farther from the time of read wordline actuation) will only exacerbate the problem of false (“0”) detection when expecting a (“1”), under concurrent row address access scenario.
With the increasing capacity of on chip memory in the latest system on chip (SOC) designs, coupled with increased variability in the latest technology nodes, it is increasingly more likely to experience an occurrence of a memory cell with an incorrect read of a logic high (“1”) due to noise injected by the write port and an unintended discharge of the RBL to either the uncertainty region or to the detect logic low (“0”) region.
It is also recognized that a DPRF memory can be configured such that the latch and write ports are supplied with a different voltage compared to the read port, in order to save dynamic power. The reason for this is that the latch and write portion of the memory cell is susceptible to a stability and writability issue, while the read port is not. So, in the case of a low power mode of operation, the read port voltage is lowered to as low a value as permissible by the required performance, while simultaneously constraining the latch and write port voltage to a higher value than read port voltage, as determined by memory cell stability and writability. The problem of a read of a logic high (“1”) with noise injected by the write port during concurrent row address acccess resulting in an undesired RBL discharge is even more prominent for this dual voltage operating scenario. This is because the voltage bounce discussed above is not reduced by virtue of the latch and write portion being at a higher voltage, but the read port will operate more slowly because of the lower supply voltage on RWL. In context of FIG. 4, this will result in line 56 having lesser slope (i.e. becoming closer to horizontal). Thus, the time of bit line level evaluation has to be further delayed (past point 52) corresponding to line 56 having crossed the uncertain region for a successful read of logic low (“0”) from the latch. But this also increases the chance of the write port noise causing a discharge of the RBL when making a read of a logic high (“1”) to the extent of the uncertain detection range (or even to the detect logic low (“0”) region), as although the unwanted discharge of the RBL should also become slower because of lower RWL level, it may become less slow than the case when RBL has to discharge, because of different worse case mismatch combinations of the read port devices dictating the design for two scenarios. Effectively, this means that the longer the wait for evaluating RBL level for a read logic low (“0”), higher the unwanted RBL discharge level for a read logic high (“1”).
One solution to the problem noted above, which is specifically an issue when the DPRF memory array 30 is organized as column mux>1, is to instead organize the DPRF memory array 30 as column mux=1. This solution is not desirable at least because the column mux=1 organization is very restrictive in terms of aspect ratio constraining the physical placement of embedded memories inside the SOC, and also because the column mux=1 increases the susceptibility of the DPRF memory to multiple bit failures per word due to radiation (soft errors), and hence poses a requirement of very costly multiple bit error correction schemes. Single bit error correction schemes are normally deemed sufficient for tackling soft errors for memory array organization of column mux>1, thus making it a preferred configuration over column mux=1, in applications sensitive to radiation errors.
In another solution to the problem noted above, the transistor 24 of the read port is weakened in order to reduce the susceptibility of RBL bounce on the complement node 18 during a read of a logic high (“1”). This solution is not desirable at least because weakening of transistor 24 by increasing transistor length introduces manufacturing complexity as polysilicon pitch has various restrictions in latest technologies. Also weakening of transistor 24 impacts the read current as well as increases variability of read current (if the weakening of transistor 24 is accomplished by transistor width reduction). This leads to significant performance degradation across the voltage range, making this memory cell unsuitable for applications requiring high dynamic operating voltage range along with high performance at higher voltages (e.g., mobile phone chipsets).
There is accordingly a need in the art for a DPRF cell and memory that addresses the deficiencies discussed above while supporting memory organization as a column mux>1.